Emitter-coupled logic ("ECL") circuitry has been widely used in the industry for many years. In ECL, a pair of switching transistors operate in push-pull, with their emitters coupled-together to a switching state current source. Because the switching transistors in ECL are always in an active region, on a relative basis ECL changes states rapidly, but dissipates a large amount of power.
FIG. 1A depicts a typical ECL circuit, coupled between upper and lower rail power supplies Vcc (typically 0 VDC), Vee (typically -5.2 VDC or -4.5 VDC, depending upon fabrication process) and coupled to receive a switching-current setting voltage Vcs. Vcs is typically about one and one-half emitter-base voltage drops (e.g., about 1.5 VDC) more positive than Vee.
An input signal, typically varying between a "1" level of -0.8 V and a "0" level of -1.6 V, is coupled to the base of transistor Q1, and a Vbb bias voltage of typically--1.2 V is coupled to the base of transistor Q2. Transistor Q3 is biased by a voltage Vcs to act as a current source for transistors Q1 or Q2, which transistors function in push-pull, and to establish a switching state current level that will prevent Q1 and Q2 from saturating. It is noted that voltage signals in ECL circuitry are referenced to ECL ground, which is typically the upper rail power supply Vcc.
When the input voltage is "1", e.g., more positive than Vbb, current flow in Q1 increases and current flow in Q2 decreases in push-pull fashion. The resultant increase in voltage dropped across collector load resistor R1 is coupled to transistor Qpu, and appears as an inverted output voltage signal at the output ("OUT") node. (Of course, the voltage dropped across collector load resistor R2 decreases because of the push-pull configuration of Q1-Q2.) Transistor Qpu functions as an emitter follower, whose emitter load is the current source Qpd and a parallel load capacitance CL (denoted in phantom).
It will be appreciated the ECL circuit of FIG. 1A actively pulls-up the output signal during a "0" to "1" output voltage transition because Qpu's low output impedance permits CL to rapidly charge up to the "1" voltage level. However the ECL circuit of FIG. 1A only passively pulls-down the output during a "1" to "0" output voltage transition because the voltage across CL discharges into Qpd's relatively high output impedance, which prolongs the output voltage transition.
FIG. 1B depicts this "fast pull-up, slow pull-down" output voltage characteristic. In FIG. 1B (as in FIGS. 2B and 3B), the "0" to "1" to "0" state input voltage signal is shown in phantom, and the "1" to "0" to "1" state output voltage signal is shown for various load conditions. It is noted that when CL is small, e.g., 0.04 pF, the output voltage essentially is an inverted version of the input voltage. However, as CL increases to 0.5 pF and then to 1.0 pF, the "1" to "0" output voltage transition takes considerably longer. FIG. 1C depicts the pull-down current through Qpd. As shown, Vcs and R3 establish an essentially steady-state pull-down current of perhaps 250 .mu.A in Qpd, with slight glitches occurring during the output voltage transition times. The basic circuit of FIG. 1A will be referred to herein as "ECL".
FIG. 2A depicts one prior art attempt to improve the pull-down output voltage characteristics of an ECL circuit, wherein Qpd functions as an active pull-down output transistor. In FIG. 2A, Q1, Q2, Q3 and Qpu operate as described above. As the input voltage transitions "0" to "1", the voltage across R2 transitions similarly, which transition is AC-coupled via capacitor C1 to the base of transistor Qpd. The resultant positive-going voltage transient at the base turns-on Qpd, reducing its output impedance, which allows the voltage across load capacitance CL to discharge rapidly through Qpd. The AC-coupled active pull-down ECL configuration of FIG. 2A will be referred to herein as "AC-APD".
FIG. 2B depicts the relative improvement afforded by an AC-APD technique, wherein the circuit has been optimized for a load CL=0.5 pF, e.g., CL.sub.optimum =0.5 pF (e.g., C1=0.2 pF, C2=1 pF). Note the improvement, for example, in the output waveform in FIG. 2B compared to the output waveform of FIG. 1B for the case CL=0.5 pF. However in AC-APD configurations, the values of C1, C2 and R3 are preferably optimized for a specific CL loading condition, as these components determine the dynamic pull-down current in Qpd. Thus, as shown in FIG. 2B, the output waveform is improved for the optimized condition CL=0.5 pF, but not for CL&gt;0.5 pF. Stated differently, for a given AC-APD design, there is a finite range of loadings, outside of which proper circuit operation cannot be ensured. Unfortunately, it is not feasible in practice to fine tune mass-produced AC-APD circuits to various load conditions to achieve a good "1" to "0" output voltage transition.
FIG. 2C depicts the pull-down current through Qpd for the AC-APD configuration of FIG. 2A, and shows the current transient occurring when the AC-coupled transient turns-on Qpd. For CL&lt;CL.sub.optimum, the excess pull-down current is consumed as crossover current, resulting in wasteful power dissipation. For CL&gt;CL.sub.optimum, the initial pull-down transition is fast, followed by a slowly discharging tail, dictated by the steady-state current in Qpd, see voltage waveform 2 in FIG. 2B, for example.
In a gate-array environment where circuit loading uncertainties will exist, a sufficiently large dynamic and steady-state pull-down current should be maintained in an AC-APD macro-cell. Unfortunately, the necessity to maintain such pull-down current dissipates excessive power in the macrocell. Further, having to provide relatively large capacitors C2 (typically in the pF range), and resistors R3 (typically several tens of K.OMEGA.) brings a significant chip area penalty and added fabrication process complexity. Understandably, the resultant increase in cell size degrades chip performance and increases interconnection-imposed delays.
What is needed is an ECL-type circuit that provides active output voltage pull-down without significant increase in chip size, process fabrication, or power dissipation. Preferably the pull-down improvement provided by such circuit should be substantially independent of loading conditions. Further, such circuit should provide an output voltage whose falltime may be controlled to be symmetrical to the risetime, thus minimizing timing skew.
The present invention discloses such a circuit.